Poras T. Balsara @ UT-Dallas

Book

R. B. Staszewski and P. T. Balsara: “All-Digital Frequency Synthesizer in Deep-Submicron CMOS,” Wiley-Interscience, John Wiley & Sons, Hoboken, New Jersey, Sept. 2006. ISBN 0-471-77255-0.

Some Recent Publications

C. K. Singh, N. Al-Dhahir and P.T. Balsara: “Effect of Word-length Precision on the Performance of MIMO Systems,” to appear in the IEEE International Conference on Circuits and Systems (ISCAS), New Orleans, LA, 2007.

V. Parikh, P.T. Balsara and O. Eliezer: “A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters,” to appear in the IEEE International Conference on Circuits and Systems (ISCAS), New Orleans, LA, 2007.

C. Singh, S. Honnavara Prasad and P.T. Balsara: “VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition,” Proceedings of the 20^th IEEE International Conference on VLSI Design (VLSI ‘07), Bangalore, India. Jan. 6-10, 2007, pp. 836-841.

I. Elahi, K. Muhammad & P. T. Balsara: “IIP2 and DC Offsets in the Presence of Leakage at LO Frequency,” IEEE Transactions on Circuits and Systems-II, vol. 53, No. 8, Aug. 2006, pp. 647-651

I. L. Syllaios, P. T. Balsara & O. Eliezer: “A Generalized Signal Reconstruction Method for Designing Interpolation Filters,” Proceedings of the IEEE International Conference on Circuits and Systems (ISCAS), Kos, Greece, May 2006, pp. 5768-5771.

M. J. Akhbarizadeh, M. Nourani, Deepak-Sarathi V., & P. T. Balsara: “A Non-Redundant Ternary CAM Circuit for Network Search-Engines,” IEEE Transactions on VLSI Systems, vol. 14, No. 3, March 2006, pp. 268-278.

R. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg & P. T. Balsara: “1.3V 20ps Time-to-Digital Converter in 90nm CMOS,” IEEE Transactions on Circuits and Systems-II, vol. 53, No. 3, March 2006, pp. 220-224.

I. Elahi, K. Muhammad & P. T. Balsara: “I/Q Mismatch Compensation Using Adaptive Decorrelation in a Low-IF Receiver in 90nm CMOS Process,” IEEE Journal on Solid-State Circuits, vol. 41, No. 2, February 2006, pp. 395-404.

V. Ramakrishnan and P.T. Balsara: “A Wide-Range High-Resolution Compact CMOS Time to Digital Converter,” Proceedings of the 19^th IEEE International Conference on VLSI Design (VLSI ‘06), Hyderabad, India, January 3-7, 2006, pp. 197-202.

R. Staszewski, Chan Fernando & P. T. Balsara: “Event-Driven Simulation and Modeling of an RF Oscillator,” IEEE Transactions on Circuits and Systems-I, Vol. 52, No. 4, April 2005, pp. 723-732.

M. Chugh, D. Bhatia & P. T. Balsara: “Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA,” 12^th Reconfigurable Architectures Workshop (RAW 2005), Denver, Colorado, April 4-5, 2005. pp. 1-8.

R. Staszewski, & P. T. Balsara: “Phase-Domain All-Digital Phase-Locked Loop,” IEEE Transactions on Circuits and Systems-II, Vol. 52, No. 3, March 2005, pp. 159-163

I. Elahi, K. Muhammad & P. T. Balsara: “I/Q Mismatch Compensation in a low-IF Receiver in 90nm CMOS Process,” Proceeding of the IEEE International Solid-State Circuits Conference, San Francisco, CA, February 6-10, 2005.

R. Vilangudipitchai & P. T. Balsara: “Power Switch Network Design for MTCMOS,” 18^th International Conference on VLSI Design (VLSI ‘05), Kolkata, India, January 2005. pp. 6C:1-4.

R. Bharadwaj, R. Konar, P. T. Balsara & D. Bhatia: “Exploiting Temporal Idleness to Reduce Leakage Power in Programmable Architectures,” Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, Jan. 18-21, 2005. pp. 651-656.

R. B. Staszewski, K. Muhammad, D. Leipold, C-M Hung, Y-C Ho, J. Wallberg, C. Fernando, K. Maggio, R. Staszewski, J. Koh, S. John, I. Deng, V. Sarda, O. Moreira, V. Mayega, R. Katz, O. Friedman, O. Eliezer & P. T. Balsara: “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130 nm CMOS Process,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, Dec. 2004, pp. 2278-2291

M. J. Akhbarizadeh, M. Nourani, Deepak-Sarathi V., & P. T. Balsara: “PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks,” Proceedings of the IEEE International Conference on Computer Design (ICCD), San Jose, CA, Oct. 11-13, 2004. pp. 6-11.

R. Vilangudipitchai & P. T. Balsara: “Decap Aware Sleep Transistor Design,” Proceedings of the IEEE Dallas/CAS Workshop, Richardson, TX, September 27, 2004, pp. 171-175.

Nagaraj NS, T. Bonifield, A. Singh, R. Griesmer, & P. T. Balsara: “Interconnect Modeling for Copper/Low-k Technologies”, 17^th International Conference on VLSI Design (VLSI `04), Mumbai, India, January 2004, pp. 425-427.

R. Staszewski, D. Leipold, & P. T. Balsara: “Just-In-Time Gain Estimation of an RF Digitally-Controlled Oscillator for Digital Direct Frequency Modulation,” IEEE Transactions on Circuits and Systems-II, Vol. 50, No. 11, Nov. 2003, pp. 887-892

R. Staszewski, C-M Hung, D. Liepold & P. T. Balsara: “A First Multi-GHz Digitally Controlled Oscillator For Wireless Applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 51, No. 11, Nov. 2003, pp. 2154-2164.

L. Holla, P. Vallur, P. T. Balsara, A. Navada & S. Shastry: “A Fast 16-bit TSPC Adder in SOI CMOS,” Proceedings of the 7^th IEEE VLSI Design and Test Workshop, Bangalore, India, Aug. 28-30, 2003, pp. 55-60.

C. Connell & P. T. Balsara: “A New Ternary MVL Based Completion Detection Method for the Design of Self-Timed Circuits Using Dynamic CMOS Logic,” Midwest Symposium on Circuits and Systems, 2002, pp. I-503 - I-506.

Nagaraj NS, P. T. Balsara & C. Cantrell: "Modeling Parasitic Coupling Effects in Reliability Verification", Tutorial presented at the IEEE VLSI Design Conference (VLSI `02), January 2002.

K. Muhammad, R. Staszewski, & P. T. Balsara: "Challenges in Integrated CMOS Transceivers for Short Distance Wireless", Great Lakes VLSI Symposium, 2001 (Invited), pp. 45-50.

R. Staszewski, K. Muhammad & P. T. Balsara: "A Constrained Asymmetry LMS Algorithm for PRML Disk Drive Read Channels", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 48, No. 8, August 2001, pp. 793-798.

K. Muhammad, R. Staszewski & P. T. Balsara: "Speed, Power, Area and Latency Tradeoffs in Adaptive FIR Filtering for PRML Read Channels", IEEE Transactions on VLSI Systems, Vol. 9, No. 1, February 2001, pp. 42-51.

Nagaraj NS, P. T. Balsara & C. Cantrell: "Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations", 13th IEEE VLSI Design Conference (VLSI `01), January 2001.

R. Staszewski, K. Muhammad & P. T. Balsara: “A 550 Msps 8-Tap FIR Digital Filter for Magnetic Recording Read Channel,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, August 2000, pp. 1205-121.

U. Ko & P. T. Balsara: "High Performance, Energy Efficient D Flip-flop Circuits", IEEE Transactions on VLSI Systems, Vol. 8, No. 1, February 2000, pp. 94-98.

K. Rath, S. Tangirala, P. Friel, P. T. Balsara, J. Flores & J. Wadley: “Reconfigurable Array Media Processor (RAMP),” IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’00), 2000, pp. 287-288.